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ADL5315
EVALUATION BOARD
GND
L1
0 Ω
ADL5315
I PD
C4
OPEN
C3
390pF
R4
4k Ω
SW1
1
2
INPT
VSET
IOUT 8
NC 7
R5
OPEN
R3
0 Ω
I OUT
V SET
R1
100 Ω
3
SREF
VPOS 6
R2
10k Ω
C1
0.01 μ F
V POS
C2
0.01 μ F
4
COMM
RLIM 5
S REF
Figure 35. Evaluation Board Schematic (Rev. A)
Table 4. Evaluation Board (Rev. A) Configuration Options
Component
VPOS, GND
INPUT, L1, C4
R4, C3
SREF, VSET, SW1,
R1, R6, R7
IOUT, R5
R2
C1, C2, R3
Function
Supply and ground connections.
Input Interface: The evaluation board is configured to accept an input current at the
SMA connector labeled INPUT. Filtering of this current can be done using L1 and C4.
Input Compensation. Provides essential HF compensation at the INPT pin.
INPT Bias Voltage. The dc voltage applied to VSET determines the voltage at INPT,
V SET = V INPT . Connecting SREF to VSET sets the bias at INPT to be 1 V below V POS .
Opening SW1 allows for VSET to be driven externally via the SMA connector.
Output/Mirror Current Interface: The output current at the SMA connector labeled IOUT is
equal to the value at INPT. R5 allows a resistor to be installed for applications where a
scaled voltage referenced to IPD is desirable instead of a current.
Current Limiting. An external resistor to VPOS sets the current limit at INPT from
1 mA to 16 mA. I LIM = 48 V/(R LIM + 3 kΩ). The evaluation board is configured such that
I LIM = 3.7 mA.
Supply Filtering/Decoupling.
Default Conditions
Not applicable
L1 = 0 Ω (size 0805)
C4 = open (size 00603)
C3 = 390 pF (size 0805)
R4 = 4.02 kΩ (size 0402)
SW1 = closed
R1 = 100 Ω (size 0402)
R6 = R7 = 0 Ω (size 0402)
R5 = open (size 0603)
R2 = 10 kΩ (size 0402)
C1 = 0.01 μF (size 0402)
C2 = 0.1 μF (size 0603)
R3 = 0 Ω (size 0805)
Figure 36. Component Side Layout
Rev. 0 | Page 16 of 20
Figure 37. Component Side Silkscreen
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